All references cited in this specification, and their references, are incorporated by reference herein where appropriate for teachings of additional or alternative details, features, and/or technical background. More specifically, U.S. Pat. No. 7,741,921 “Trigger-Mode Distributed Wave Oscillator” (TMDWO) of Ismailov, US Pub. 2012/0169427, “Force-Mode Distributed Wave Oscillator and Amplifier Systems” (FMDWO) of Emira, and U.S. application Ser. No. 12/374,165 “Pumped Distributed Wave Oscillator System” (PDWO) of Tekin are incorporated by reference which form the core oscillators of this application.
Disclosed is a Traveling Wave Based High Speed Sampling System. This is in response to today's many communication and data interface systems that employ sampling system front-ends to represent analog-in-nature continuous signals around us as digital stream of samples with best approximation to the original analog-in-nature signal.
Within a spectrum ranging from the likes of SERDES (Serializer-Deserializer) serial communication links to Digital to Analog Converters (DACs), these systems require well defined time intervals to represent the target signal without corrupting the content. With the ever increasing signal speeds, the accuracy of these timing signals defining the sampling event becomes more and more critical in the overall system performance. The sampling circuitry disclosed herein employ fully-symmetric dual-loop traveling wave oscillators such as the TMDWO, FMDWO and PDWO for enabling architectures that represent original target signals without corrupting the content.
Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly. In non-dock-forwarded communications systems, data streams are transmitted to receivers without transmitting separate, distinct dock signals. In such systems, a receiver can perform dock-and-data-recovery (CDR) processing to recover a clock signal from each data stream, where the dock signal is derived based on the timing of the data represented in the data stream. A typical CDR circuit comprises a sampling clock generator, such as a phase-locked loop (PLL) or a delay-locked loop (DLL) that generates one or more sampling clocks used to sample the received data stream. In some communications systems, a single receiver may receive multiple, different data streams, potentially having different data rates. Such a receiver will typically have a different CDR circuit for each different data stream. Implementing multiple CDR circuits, each with its own sampling clock generator can require too much layout area and/or operating power for some integrated circuit applications.
In U.S. Pat. No. 7,599,457 B2 Johnson, et al., describe a clock-and-data-recovery (CDR) system has a multi-phase dock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered dock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock Input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered dock signal is generated from the selected phase-offset clock signal.
More specifically, Johnson, et al., show a block diagram of a clock-and-data-recovery (CDR) system 100 as depicted in FIG. 1. CDR system 100 has a multi-phase dock generator 10 and N CDR channel circuits 20.1-20.N, where N Clock generator 10 generates a multi-phase set of clock signals 35 (i.e., multiple versions of a dock signal sequentially separated from each other in phase over one dock period by a specified phase-offset increment). For example, in one implementation, clock generator 10 generates 16 clock signals, each having the same frequency, but separated in phase from the previous dock signal by about 22.5 degrees. Clock signals 30 are all applied to each CDR channel circuit 20.1-20.N, which uses the set of clock signals 30 to generate a (different) recovered dock signal 40.1-40.N and a (different) output data 50.1-50.N stream from a corresponding (different) input data signal 60.1-60.N, potentially having different data rates.
It will be known to those skilled in the art that one of the intensively used digital CDR architectures is the over sampling CDR (OSCDR). It samples the received data at a rate higher than the data rate. As explained by Nobunari Tsukamoto, et al., in EP 1,898,548 A1, input data is sampled by multi-phase clock signals generated from a reference clock to obtain a bit string of samples for each data bit. A digital phase picking (DPP) algorithm selects which sample is the optimum to be used as the received data.
Usually, a phase locked loop (PLL) or a delay locked loop (DLL) circuit is used to generate the multi-phase docks necessary for oversampling. In a PLL, a ring voltage controlled oscillator (VCO) can be used to generate the required multi-phase clocks. This is implemented using delay elements (inverters) in a feedback fashion. In a DLL, delay elements are also used but in a feed-forward fashion. In order to support higher data rates, the phase difference of the required multi-phase clocks becomes very small and hence the individual delay of delay elements becomes very small also. That small delay can be beyond the technology limit or can result in a considerable amount of power consumption. This can be mitigated at the circuit level by using circuit techniques including reducing power consumption, or on the system level using architectural techniques via multiple channels.
In order to achieve very high data rates in a technology with limited circuit speed, parallelism has been applied using a multi-phase oscillator and distributed interleaved samplers as shown by Amoud Van der Wel et al., in EP 2,469,714 A1. The VCO is built using identical structural cells coupled in a ring providing multi-phase docks. The feedback loop includes data samplers, that receive the multi-phase docks, and a phase detector coupled to a phase alignment circuit receiving output signals generated by the data samplers and generating control signals to the VCO.
Many high speed serial communication standards require supporting more than one data rate. Thus, the oversampling interval changes with different data rates. For example, in PCI Express (Peripheral Component Interconnect Express, bus standard) 3 data rates are supported: 2.5 Gbps, 5 Gbps, and 8 Gbps. This results in 1 unit interval (UI) of 400 ps, 200 ps, and 125 ps, respectively. For an oversampling ratio of 8, the multi-phase dock intervals are 50 ps, 25 ps, and 15.625 ps respectively. This is more than 3× of change between the minimum and maximum oversampling dock intervals. Generally, the variation of the delay value in the delay element used in a PLL or a DLL is small and thus it is difficult to support different data rates. An oversampling circuit that can switch between oversampling intervals is described in U.S. Pat. No. 8,537,947 B2. A phase difference of the multi-phase serial data is set to be a sum of an oversampling interval and an integral multiple of a phase difference of the multi-phase docks. Thus, speed of the delay elements for generating the multi-phase serial data and speed of circuits for generating the multi-phase oversampling docks can be eased that leads to reduction of the power consumption.
In U.S. Pat. No. 8,340,619 Alireza Shirvanl-Mahdavi et al., describe “Phase synchronization of Phased Array or Multiple Receiver/Transmitter Systems,” in which a prior art system 200 is shown (FIG. 2) for generating different phases of a local oscillator signal in accordance with a conventional technique. System 200 includes a local oscillator (LO) 210, a phase generator 220, and transceiver blocks 230a-230c. Local oscillator 210 is configured to generate a local oscillator signal, such as a high frequency local oscillator signal. Phase generator 220 receives the local oscillator signal, generates all the required phases of the local oscillator signal, and distributes the LO signals with different phases to each transceiver block 230a-230c. 
According to Alireza Shirvani-Mahdavi et al., four local oscillator signals with four different phases are generated. Each local oscillator signal is transmitted to each transceiver block 230a-230c through a distribution line. However, having a distribution line for sending each phase to each transceiver block 230a-230c requires a lot of area. Also, each distribution line generally needs to be of an equal length to provide the LO signal to transceiver blocks 230a-230c with accurate phases. For example, a LO signal with a first phase is sent to all three transceiver blocks 230a-230c. If a distribution line to transceiver block 230c is longer than a distribution line to transceiver block 230a, then the LO signal received at transceiver block 230c will have a different phase from the LO signal received at transceiver block 230a. Thus, an accurate phase shifted LO signal has not been provided to each transceiver blocks 232a-230c. An additional problem with using distribution lines is that coupling between the distribution lines may alter the phases of the LO signals. Alireza Shirvani-Mahdavi et al., therefore, propose in one embodiment, a local oscillator configured to generate an LO signal. A transmission line receives the LO signal from the local oscillator and transmits the LO signal. A first set of taps and a second set of taps tap the transmission line to receive the LO signal. A plurality of transceiver blocks is configured to receive and transmit a plurality of phase-shifted radio frequency signals. Each transceiver block is coupled to a first tap and a second tap. Each LO signal received for a transceiver block is received with a different phase. However, the same reference phase may be calculated from a first LO signal received from the first tap and a second LO signal received from a second tap. Each transceiver block receives the reference LO signal having the reference phase determined from the first LO signal and the second LO signal.
Prior art has certainly shown improvements in an attempt to represent analog-in-nature continuous signals as digital streams of sample packets having the characteristics of the original signal as dose as possible. Primarily this has been achieved by resorting to such techniques as forming well defined time intervals and traveling wave based specific multi-phase sampling methods, especially as the demand for faster data rates has been increasing. However, prior art has been mostly using delay based ring oscillators. What is needed is a system comprising fully-symmetric dual-loop traveling wave oscillators configured in a manner described further below in the Detailed Description section of the present disclosure.